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2.5v or 3.3v,10- 220 mhz, low jitter, 5 output zero dela y buffe r CY23EP05 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07759 rev. *b revised december 13, 2005 features ? 10 mhz to 220 mhz maximum operating range ? zero input-output propagation delay, adjustable by loading on clkout pin ? multiple low-skew outputs ? 30 ps typical output-output skew ? one input drives five outputs ? 22 ps typical cycle-to-cycle jitter ? 13 ps typical period jitter ? standard and high drive strength options ? available in space-saving 150-mil soic package ? 3.3v or 2.5v operation ? industrial temperature available functional description the CY23EP05 is a 2.5v or 3.3v zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin soic package. it accepts one reference input, and drives out five low-skew clocks. the -1h version operates up to 220 (200) mhz frequencies at 3.3v (2.5v), and has a higher drive strength than the -1 devices. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the CY23EP05 pll enters a power-down mode when there are no rising edges on the ref input (<~2 mhz). in this state, the outputs are three-stated and the pll is turned off, resulting in less than 25 a of current draw. the CY23EP05 is available in different configurations, as shown in the ordering information table. the CY23EP05-1 is the base part. the CY23EP05-1h is the high-drive version of the -1, and its rise and fall times are much faster than the -1. these parts are not intended fo r 5v input-tolerant applications block diagram pin configuration 1 2 3 4 5 8 7 6 ref clk2 clk1 gnd v dd clkout clk4 clk3 top view pll ref clk1 clk2 clk3 clk4 clkout
CY23EP05 document #: 38-07759 rev. *b page 2 of 12 zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. the output driving the clkout pin will be driving a total load of 5 pf plus any additional load externally connected to this pin. for applications requiring zero input-output delay, the total load on each output pin (including clkout) must be the same. if input-output delay adjustments are required, the clkout load may be changed to vary the delay between the ref input and remaining outputs. for zero output-output skew, be sure to load all outputs equally. for further information refer to the application note titled ?cy2305 and cy2309 as pci and sdram buffers?. notes: 1. weak pull-down. 2. weak pull-down on all outputs. 3. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. pin description pin signal description 1ref [1] input reference frequency 2clk2 [2] buffered clock output 3clk1 [2] buffered clock output 4 gnd ground 5clk3 [2] buffered clock output 6v dd 3.3v or 2.5v supply 7clk4 [2] buffered clock output 8 clkout [2,3] buffered clock output, internal feedback on this pin
CY23EP05 document #: 38-07759 rev. *b page 3 of 12 absolute maximum conditions supply voltage to ground potent ial ................. ?0.5v to 4.6v dc input voltage...................................... v ss ? 0.5v to 4.6v storage temperature .............. .............. ........ ?65c to 150c junction temperature .................................................. 150c static discharge voltage (per mil-std-883, method 3015. ............ .............. ... > 2000v operating conditions parameter description min. max. unit v dd3.3 3.3v supply voltage 3.0 3.6 v v dd2.5 2.5v supply voltage 2.3 2.7 v t a operating temperature (ambient temperature)?commercial 0 70 c operating temperature (ambient temperature)?industrial ?40 85 c c l [4] load capacitance, <100 mhz, 3.3v ? 30 pf load capacitance, <100 mhz, 2.5v with high drive ? 30 pf load capacitance, <133.3 mhz, 3.3v ? 22 pf load capacitance, <133.3 mhz, 2.5v with high drive ? 22 pf load capacitance, <133.3 mhz, 2.5v with standard drive ? 15 pf load capacitance, >133.3 mhz, 3.3v ? 15 pf load capacitance, >133.3 mhz, 2.5v with high drive ? 15 pf c in input capacitance [5] ?5pf bw closed-loop bandwidth (t ypical), 3.3v 1?1.5 mhz closed-loop bandwidth (typical), 2.5v 0.8 mhz r out output impedance (typical ), 3.3v high drive 29 ? output impedance (typical), 3.3v standard drive 41 ? output impedance (typical ), 2.5v high drive 37 ? output impedance (typical), 2.5v standard drive 41 ? t pu power-up time for all vdd?s to reach minimum specified voltage (power ramps must be monotonic) 0.01 50 ms theta ja [6] dissipation, junction to ambient, 8-pin soic 131 c/w theta jc [6] dissipation, junction to case, 8-pin soic 81 c/w 3.3v dc electrical specifications parameter description test conditions min. max. unit v dd supply voltage 3.0 3.6 v v il input low voltage ? 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input leakage current 0 < v in < v il ?10 a i ih input high current v in = v dd ? 100 a v ol output low voltage i ol = 8 ma (standard drive) i ol = 12 ma (high drive) ? ? 0.4 0.4 v v v oh output high voltage i oh = ?8 ma (standard drive) i oh = ?12 ma (high drive) 2.4 2.4 ? ? v v i dd (pd mode) power down supply current ref = 0 mhz (commercial) ? 12 a ref = 0 mhz (industrial) ? 25 a i dd supply current unloaded outputs, 66-mhz ref ? 30 ma notes: 4. applies to test circuit #1. 5. applies to both ref clock and internal feedback path on clkout. 6. theta ja, eia jedec 51 test board conditions, 2s2p; theta jc mil-spec 883e method 1012.1.
CY23EP05 document #: 38-07759 rev. *b page 4 of 12 2.5v dc electrical specifications parameter description test conditions min. max. unit v dd supply voltage 2.3 2.7 v v il input low voltage ? 0.7 v v ih input high voltage 1.7 v dd + 0.3 v i il input leakage current 0133.3 mhz 40 ? 60 % t 2 t 1 output duty cycle [8] <133.3 mhz 47 ? 53 % >133.3 mhz 45 ? 55 % t 3, t 4 rise, fall time (3.3v) [8] std drive, cl = 30 pf, <100 mhz ? ? 1.6 ns std drive, cl = 22 pf, <133.3 mhz ? ? 1.6 ns std drive, cl = 15 pf, <167 mhz ? ? 0.6 ns high drive, cl = 30 pf, <100 mhz ? ? 1.2 ns high drive, cl = 22 pf, <133.3 mhz ? ? 1.2 ns high drive, cl = 15 pf, >133.3 mhz ? ? 0.5 ns t 3, t 4 rise, fall time (2.5v) [8] std drive, cl = 15 pf, <133.33 mhz ? ? 1.5 ns high drive, cl = 30 pf, <100 mhz ? ? 2.1 ns high drive, cl = 22 pf, <133.3 mhz ? ? 1.3 ns high drive, cl = 15 pf, >133.3 mhz ? ? 1.2 ns t 5 output to output skew [8] all outputs equally loaded ? 30 100 ps t 6 delay, ref rising edge to clkout rising edge [8] pll enabled @ 3.3v ?100 ? 100 ps pll enabled @2.5v ?200 ? 200 ps t 7 part to part skew [8] measured at v dd /2. any output to any output, 3.3v supply ??150ps measured at v dd /2. any output to any output, 2.5v supply ??300ps notes: 7. for the given maximum loading conditions. see c l in operating conditions table. 8. parameter is guaranteed by design and charac terization. not 100% tested in production.
CY23EP05 document #: 38-07759 rev. *b page 5 of 12 t lock pll lock time [8] stable power supply, va lid clocks presented on ref and clkout pins ??1.0ms t jcc [8,9] cycle-to-cycle jitter, peak 3.3v supply, >66 mhz, <15 pf ? 22 55 ps 3.3v supply, >66 mhz, <30 pf, standard drive ? 45 125 ps 3.3v supply, >66 mhz, <30 pf, high drive ? 45 100 ps 2.5v supply, >66 mhz, <15 pf, standard drive ? 40 100 ps 2.5v supply, >66 mhz, <15 pf, high drive ? 35 80 ps 2.5v supply, >66 mhz, <30 pf, high drive ? 52 125 ps t per [8,9] period jitter, peak 3.3v supply, 66?100 mhz, <15 pf ? 18 60 ps 3.3v supply, >100 mhz, <15 pf ? 13 35 ps 3.3v supply, >66 mhz, <30 pf, standard drive ? 28 75 ps 3.3v supply, >66 mhz, <30 pf, high drive ? 26 70 ps 2.5v supply, >66 mhz, <15 pf, standard drive ? 25 60 ps 2.5v supply, 66?100 mhz, <15 pf, high drive ? 22 60 ps 2.5v supply, >100 mhz, <15 pf, high drive ? 19 45 ps 3.3v and 2.5v ac electrical specifications (continued) parameter description test conditions min. typ. max. unit switching waveforms note: 9. typical jitter is measured at 3.3v or 2.5v, 29c, with all outputs driven into the maximum specified load. further informatio n regarding jitter specifications may be found in the application notes, ?understanding data sheet jitter specifications for cypress products.? duty cycle timing t 1 t 2 v dd /2 v dd /2 v dd /2 all outputs rise/fall time output t 3 3.3v(2.5v) 0v 0.8v(0.6v) 2.0v(1.8v) 2.0v(1.8v) 0.8v(0.6v) t 4 output-output skew t 5 output output v dd /2 v dd /2
CY23EP05 document #: 38-07759 rev. *b page 6 of 12 switching waveforms (continued) input-output propagation delay v dd /2 t 6 input clkout v dd /2 v dd /2 v dd /2 t 7 any output, part 1 or 2 any output, part 1 or 2 part-part skew test circuits 0.1 f v dd 0.1 f v dd clk c load outputs gnd gnd test circuit # 1
CY23EP05 document #: 38-07759 rev. *b page 7 of 12 supplemental parametric information figure 1. 2.5v typical room temper ature graph for ref input to clkn delay versus loading difference between clkout and clkn. data is shown for 66 mhz. delay is a weak function of frequency. -1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500 -20 -10 0 10 20 load clkout- load clkn (pf) delay ref input to clkn (ps) 2.5v standard drive 2.5v high drive figure 2. 3.3v typical room temper ature graph for ref input to clkn delay versus loading difference between clkout and clkn. data is shown for 66 mhz. delay is a weak function of frequency. -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -20 -10 0 10 20 load clkout- load clkn (pf) delay ref input to clkn (ps) 3.3v standard drive 3.3v high drive
CY23EP05 document #: 38-07759 rev. *b page 8 of 12 figure 3. 2.7v measured supply current versus frequency, drive strength, loading, and temperature. note that the 30-pf data above 100 mhz is beyond the data sheet specification of 22 pf. 0 10 20 30 40 50 60 70 33 66 100 133 166 200 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30pf, 90c, high drive figure 4. 3.6v measured supply current versus frequenc y, drive strength, loading, and temperature. note that the 30-pf high-drive data above 100 mhz is beyond the data sheet specification of 22 pf. 0 20 40 60 80 100 33 66 100 133 166 200 233 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 30pf, -45c, standard drive 30pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30 p f, 90c, hi g h drive
CY23EP05 document #: 38-07759 rev. *b page 9 of 12 figure 5. typical 3.3v measured cycle -to-cycle jitter at 29c, versus fr equency, drive strength, and loading 0 50 100 150 200 250 300 350 0 50 100 150 200 250 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 30 pf, high drive figure 6. typical 2.5v measured cycle -to-cycle jitter at 29c, versus fr equency, drive strength, and loading 0 50 100 150 200 250 300 350 400 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, hi g h drive figure 7. typical 3.3v measured period jitter at 29c, versus frequency, drive strength, and loading 0 50 100 150 200 250 0 50 100 150 200 25 0 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 30 pf, high drive figure 8. typical 2.5v measured period jitter at 29c, versus frequency, drive strength, and loading 0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 p f, hi g h drive
CY23EP05 document #: 38-07759 rev. *b page 10 of 12 -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz figure 9. 100 mhz (top) and 156.25 mhz (bo ttom) typical phase-noise data versus v dd and drive strength [9]
CY23EP05 document #: 38-07759 rev. *b page 11 of 12 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. ordering information ordering code package type operating range lead-free CY23EP05sxc-1 8-pin 150-mil soic commercial CY23EP05sxc-1t 8-pin 150-mil soic ? tape and reel commercial CY23EP05sxi-1 8-pin 150-mil soic industrial CY23EP05sxi-1t 8-pin 150-mil soic ? tape and reel industrial CY23EP05sxc-1h 8-pin 150-mil soic commercial CY23EP05sxc-1ht 8-pin 150-mil soic ? tape and reel commercial CY23EP05sxi-1h 8-pin 150-mil soic industrial CY23EP05sxi-1ht 8-pin 150-mil soic ? tape and reel industrial package drawing and dimensions seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c 8-lead (150-mil) soic s8
CY23EP05 document #: 38-07759 rev. *b page 12 of 12 document history page document title: CY23EP05 2.5v or 3.3v, 10-220 -mhz, low jitter, 5 output zero delay buffer document number: 38-07759 rev. ecn no. issue date orig. of change description of change ** 349620 see ecn rgl new data sheet *a 401073 see ecn rgl updated delay vs. load graph with standard drive data added phase-noise graph *b 413826 see ecn rgl minor change: typo - changed from CY23EP05sxc-t to CY23EP05sxc-1t

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